DATE 2010 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information

Scope

The Design, Automation, and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. The conference includes plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days, and a track for executives. Friday Workshops are focusing on emerging research and application topics. At DATE 2010, one of the Friday Workshops is devoted to 3D Integration. This one-day event consists of a plenary keynote, regular and poster presentations, and a panel session.

3D Integration is a promising technology for extending Moore’s momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. But in order to produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges. The first edition of this workshop took place in conjunction with DATE 2009 (see http://www.date-conference.com/conference/date09-workshop-W5).

You are invited to participate and submit your contributions to the DATE 2010 Friday Workshop on 3D Integration. The areas of interest include (but are not limited to) the following topics:

3D technologies: chip-on-chip, micro-bumping, contactless, and through-silicon-vias interconnect
TSV formation, perm./temp. wafer (de-)bonding
3D architectures and design space exploration
3D combinations of logic, memory, analog, RF
Application, product, or test chip case studies
3D design methods and EDA tools
Signal and power integrity, and ESD in 3D
Thermo(-mechanical) analysis and -aware design
Chip-package co-design for 3D
Test, design-for-test, and debug techniques for 3D
Wafer test access, KGD test, thin-wafer handling
Economic benefit/cost trade-off studies
Standardization initiatives

Submissions

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Submissions are invited in the form of (extended) abstracts not exceeding two pages and must be sent in as PDF file to yann.guillou@stericsson.com and geert.vanderplas@imec.be with “DATE10-3D-WS” as subject. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc.

Key Dates

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Paper Submission deadline: November 15, 2009
Notification of Acceptance: November 30, 2009
Camera-Ready Material due date: February 25, 2010

Additional Information

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Erik Jan Marinissen – General Chair
IMEC
Kapeldreef 75
3001 Leuven, Belgium
E-mail: erik.jan.marinissen@imec.be

Yann Guillou – Program Co-Chair
ST-Ericsson
12, rue Jules Horowitz – BP 217
38019 Grenoble cedex, France
E-mail: yann.guillou@stericsson.com

Geert Van der Plas – Program Co-Chair
IMEC
Kapeldreef 75
3001 Leuven, Belgium
E-mail: geert.vanderplas@imec.be

For more information, visit us on the web at:
http://www.date-conference.com/conference/date10-workshop-W5

The Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) is sponsored by the European Design and Automation Association, the EDA Consortium, the IEEE Computer Society (TTTC), (CEDA), ECSI, RAS and ACM SIGDA.